About
Weaver is an EDA flow targeting synthesis of asynchronous (self-timed) circuits from large possibly hierarchical high-level behavioral or structural HDL speciefications. The flow is currently primarily targeting quasi-delay-insensitive (QDI) implementations.
To take advantage of the Weaver flow your standard-cell library should be extended with specialized asynchronous micropipeline cells.
Weaver flow exploits the architectural similarity between implementations based on asynchronous micropipelines and synchronous designs. The flow uses an off-the-shelf synchronous synthesis engine for synthesizing specification in synthesizable HDL (Verilog or VHDL) into a synchronous netlist and converts it into micropipeline implementation.
Generally any synthesis engine can be used to synthesize the original behavior. Weaver-DC is currently the only version of the flow. It utilizes the Synopsys Design Compiler as a synthesis engine.
