Asynchronous Circuits & Systems Group Recent Publications
 
 

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Book chapters

K. J. Kulikowski, A. B. Smirnov, A. Taubin Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks in Workshop on Cryptographic Hardware and Embedded Systems (CHES'06) October 10-13, 2006 Yokohama, Japan [pdf]

K. J. Kulikowski, M. G. Karpovsky and A. Taubin Fault Attack Resistant Cryptographic Hardware with Uniform Error Detection in proceedings of Workshop on Fault Diagnosis and Tolerance in Cryptography 2006 (FTDC'06), October 2006, Yokohama, Japan [pdf]

K. J. Kulikowski, M. G. Karpovsky and A. Taubin DPA on Faulty Cryptographic Hardware and Countermeasures in proceedings of Workshop on Fault Diagnosis and Tolerance in Cryptography 2006 (FTDC'06), October 2006, Yokohama, Japan [pdf]

Journal publications

Tejpal Singh, Alexander Taubin, A Highly Scalable GALS Crossbar Using Token Ring Arbitration, IEEE Design & Test, September-October 2007, pp.464-472 [pdf].

Alexander Taubin, Jordi Cortadella, Luciano Lavagno, Alex Kondratyev and Ad Peeters Design Automation of Real-Life Asynchronous Devices and Systems in Foundations and Trends(r) in Electronic Design Automation - Vol.2, No.1, September, 2007., pp.1-133[pdf].

A printed and bound version of the above article is available at a 50% discount from Now Publishers. This can be obtained by entering the promotional code EDA002001 on the order form at now publishers.

Thesis

A. Smirnov, Micropipeline Synthesis System, Boston University, ECE, January 2009 [pdf]

Published conference papers

K. Kulikowski, V. Venkataraman, Z. Wang, A. Taubin, Power Balanced Gates Insensitive to Routing Capacitance Mismatch, proc. of Design, Automation and Test in Europe (DATE'08), 10-18 March 2008, Munich, Germany

K. Kulikowski, V. Venkataraman, Z. Wang, A. Taubin, M. Karpovsky, Asynchronous balanced gates tolerant to interconnect variability, proc. International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Seattle, USA

K. Kulikowski, M. Karpovsky, Z. Wang, A. Kulikowski, and A. Taubin, Concurrent Fault Detection for Secure QDI Asynchronous Circuits,2nd Workshop on Dependable & Secure Nanocomputing. In conjunction with the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, June 2008 [pdf]

A. Smirnov, A. Taubin, Synthesizing Asynchronous Micropipelines with Design Compiler, Proc. SNUG Boston 2006: Synopsys User Group, September 18-19, 2006, Boston, USA [pdf]

Tejpal Singh, Alexander Taubin, A GALS Solution Based on Highly Scalable, Low Latency, Crossbar Using Token Ring Arbitration, Proc. of The 49th IEEE International Midwest Symposium on Circuits and Systems. August, 2006 [pdf]

K. J. Kulikowski, M. G. Karpovsky, A. Taubin Power Attacks on Secure Hardware Based on Early Propagation of Data. International On-Line Testing Symposium (IOLTS'06), July 2006, Lake of Como, Italy [pdf]

K. J. Kulikowski, M. G. Karpovsky, A. Taubin Robust Codes for Fault Attack Resistant Cryptographic Hardware, Workshop on Fault Diagnosis and Tolerance in Cryptography 2005 (FTDC'05), September 2005.

A. B. Smirnov, A. Taubin, M. Su, and M. G. Karpovsky, An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library, Proc. Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 2005 [pdf]

K. Kulikowski, M. Su, A. Smirnov, A. Taubin, and M. G. Karpovsky, D. MacDonald, Delay Insensitive Encoding and Power Analysis: A Balancing Act, Proc. 11th Int. Symp. on Asynchronous Circuits and Systems, 2005 [pdf]

Workshop presentations

G. Gaubatz, B. Sunar, M. G. Karpovsky, Robust Residue Codes for Fault-Tolerant Public-Key Arithmetic, Proc of Int. Workshop on Fault Detection and Tolerance in Cryptography, 2006

A. B. Smirnov, M. G. Karpovsky, A. Taubin. On Automatic Synthesis of Data Dependent Micropipeliness in IWLS 2006 Fifteenth International Workshop on Logic and Synthesis. June 7-9, 2006. Vail, Colorado, USA

K. J. Kulikowski, M. G. Karpovsky, A. Taubin, Memories with Robust Self Error Detection Invariant to Error Distributions, In Informal Proceedings of the 10th European Test Symposium (ETS05), May 2005.

A. B. Smirnov, A. Taubin A., M. G. Karpovsky and L. Rozenblyum Gate Transfer Level Synthesis as an Automated Approach to Fine-Grain Pipelining in Workshop on Token Based Computing (ToBaCo). June 22, 2004. Bologna, Italy [pdf]

A. B. Smirnov, A. Taubin, and M. G. Karpovsky Automated Pipelining in ASIC Synthesis Methodology: Gate Transfer Level in IWLS 2004 Thirteenth International Workshop on Logic and Synthesis. June 2-4, 2004. Temecula, California, USA [pdf]

 

 
 
 
 
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